1. Field of the Invention
The present invention relates to a digital delay locked loop (DLL) circuit that is applicable to an interface circuit for a memory, such as a DRAM.
2. Description of the Related Art
The circuit delay inside an LSI fluctuates depending on the supply voltage, temperature, and variation in the process at the time of the fabrication.
The DLL circuit is used to suppress the fluctuation to thereby realize a desired stable delay.
The DLL is a technique to regulate based on its circuit configuration the amount of the delay (time difference) arising between a clock signal from the external of the chip and a clock signal inside the chip, and thereby can realize a short clock access time and a high operating frequency. The DLL circuit is used for, e.g., an interface circuit for a DRAM.
Various circuits have been proposed as this kind of DLL circuit; refer to, e.g., Japanese Patent Laid-open No. 2005-142859 (FIGS. 1 and 8) and JP-A-2004-531981 (FIGS. 1 and 3). Hereinafter referred to as Patent Document 1 and Patent Document 2, respectively.
In the DLL circuits disclosed in Patent Document 1 and Patent Document 2, feedback control for a variable delay circuit is carried out so that the variable delay circuit typically keeps a delay value that is predefined or specified by a register.